The present invention relates generally to an integrated circuit assembly, and more particularly to an assembly wherein a plurality of leadframe leads are supported on a dielectric substrate, itself defining a plurality of electrically conductive traces. The leadframe leads are electrically isolated from the conductive traces. The assembly may also include one or more electrically conductive layers supported by the substrate and used for additional electrical interconnections.
In the field of integrated circuits, the physical size of an integrated circuit assembly is a primary concern. As technology has improved and functionality of integrated circuit chips has increased, the number of electrical interconnections required by a typical individual IC chip within an integrated circuit assembly has steadily increased. Very high density electrical interconnection arrangements within the integrated circuit package are now required to provide the needed number of electrical connections to interface the integrated circuit chip to the outside world. At the same time, the need for the overall integrated circuit assembly to retain as small a footprint as possible remains a primary consideration. In the prior art, a leadframe was typically used to provide electrical connections to the IC chip. As higher numbers of connections were required, the width of individual leadframe leads was simply decreased and the spacing between the leads was also decreased, thereby increasing the number of leads per inch. This is an acceptable solution up to a point. As the width of the leads and the spacing therebetween is decreased, the IC assembly becomes increasingly more difficult to manufacture and the reliability of the assembly is reduced. Therefore, other solutions have been proposed, as will be discussed immediately below.
FIGS. 1 and 1A illustrate a prior art integrated circuit assembly generally indicated by the reference numeral 10. The assembly utilizes an arrangement which does not include a leadframe but, nevertheless attempts to achieve a high density of electrical interconnections. The assembly includes a dielectric substrate 12 having a top surface 14, a side surface 15 and a bottom surface 16. A plurality of solder balls 18 are attached to bottom surface 16 in a grid array. Substrate 12 defines a plurality of electrically conductive traces, a representative example of which is shown at reference numeral 20. Conductive trace 20 comprises a first portion 20A integral with top surface 14 of the substrate, a second portion 20B which is a via that goes through the substrate and a third portion 20C integral with the bottom surface 16 of the substrate. As may be seen in the figures, conductive trace 20 is routed from the top surface of the substrate to the bottom surface through the via 20b.
An IC chip 22 having a plurality of input/output pads 24 is supported on top surface 14 of the substrate. A plurality of bonding wires 26 electrically connect the input/output pads on IC chip 22 to the conductive traces. For example, bonding wire 26A is electrically connected to input/output pad 24A on IC 22 at one end and at its other end is electrically connected to conductive trace 20A. Solder ball 18A is electrically connected to the third portion of conductive trace 20A on the bottom surface of the substrate, whereby input/output pad 24A is electrically connected to solder ball 18A by means of bonding wire 26A, and conductive trace 20. Each respective solder ball within the grid array is electrically connected to a respective input/output pad on the IC chip in this manner.
This prior art assembly, illustrated in FIGS. 1 and 1A allows for a significant number of electrical interconnects and, since the solder balls 18 may be distributed over the entire bottom surface 18, the problems with interconnection to very fine leadframe leads, as discussed above, are avoided. Nevertheless, the number of interconnections possible using this approach is still quite limited, given the advancements in IC chip technology. As will be described hereinafter, the present invention provides for an arrangement which is capable of almost doubling the number of reliable electrical interconnections which are possible without enlarging the footprint of the IC assembly.